Blue surface

TECHNOLOGY

Design Concept

I/O Core is an optical micro-transceiver that integrates optical transmission and receiver functions onto a single chip. It is designed for short distance interconnections over multimode fibers.


It is, in essence, an optical building block that can be flexibly combined with optical components to form the basis of front-pluggable transceiver modules, midboard electro-optical module (EOM) and Co-Packaged Optical modules.


I/O Core can be developed at a lower cost than competing products, due to its unique and proprietary approach to miniaturization, integration and its multimode interface, which allows a reduction in component and mounting accuracy.


AIO Core is focused on computing applications where low power consumption and low latency are important. Therefore, in addition to 25 Gbps products, we are developing 32 Gbps and 50 Gbps NRZ optical I/O cores.

Positioning of Optical I/O Core

Positioning of Optical I/O Core

Multi mode & Passive termination
Easy & High productivity handling

Multi mode &Passive termination

Areas targeted by Optical I/O Core

Areas targeted by Optical I/O Core
 

Si photonics

Overview

The Silicon Photonics Integrated Circuit in the Optical I/O Core comprises Mach-Zehnder Interference (MZI) modulators, Germanium photodetectors, Spot Size Converters (SSC) for Laser Diode (LD) coupling and Vertical Grating Couplers.


The substrate includes a cavity and alignment markers allowing the source LD to be passively aligned and mounted into the chip.


Electrical contacts are provided on the optical integrated circuit including pads for flip-chip mounting the driver IC to the modulator, and electrical input/output terminals on the periphery.
The process uses a 300 mm SOI wafer.

Overview

High Temperature operation

In the MZI modulator, the expression for modulation efficiency is given by C × V (where C =Capacitance, V = supply voltage). As C is temperature independent and the modulation voltage is constant, the frequency band is stable over a wide temperature range. Therefore, a very stable optical output waveform with low jitter can be obtained over a wide temperature range.


A Quantum Dot Fabry-Perot laser is used as the light source. Quantum Dot lasers exhibit low temperature dependence in their L-I characteristics and can provide sufficient optical output even at very high temperatures. Also, it includes the feature that reflected return light noise is very small. Optical I/O Core can therefore be used over a wide temperature range. The light output waveform of the current product from -40 °C to 85 °C is shown.


When an Optical I/O Core is mounted around a logic LSI (e.g. a Co-Packaged Optical module) or used in a harsh environment, operation at 100 °C or higher may be required. We are developing an Optical I/O Core that operates at temperatures above 100 °C, and plan to release it in the near future.


The following images show an example of an optical output waveform at 100 °C.

optical output at high temperature
wide range temperature operation

Cost efficiency

Size

The cost of an optical transceiver can be broadly divided into device and implementation. It is sometimes said that Si photonics is cheap, because it can be mass-produced by a process equivalent to CMOS, but this is not necessarily true. In the case of silicon photonic integrated circuits, cost is determined largely by the size of the chip. By reducing the size of the chip and increasing the yield, a lower cost is achieved.
In the Optical I/O Core micro-transceiver, the optical interface area is minimized by optimizing the mounting structure, and the chip area is reduced by mounting the IC and LD as bare die. The 100 Gbps micro-transceiver chip has a size of 5 mm x 5 mm, which makes it the smallest chip in the world with this function. As shown below, this size will be further reduced in the future.


Yield

Ar immersion technology is applied to 300 mm SOI wafers. The device is designed with robustness in mind. Therefore, the characteristics in the wafer are very uniform and chips can be obtained with a very high yield.
By producing smaller chips in higher yields than anywhere else, we have succeeded in significantly reducing the cost of our Si photonic chips.

Cost efficiency
Cost efficiency
 

Packaging

Overview

Optical I/O Core consists of a Si photonic integrated circuit and substrate, on which ICs and LDs are mounted, and optical coupling structures called optical pins, which allow optical fibers to be connected to the chip robustly and with low loss. Optical pins are vertical optical waveguides made of resin and fabricated using photolithographic processes. The LD is positioned and mounted with high precision using passive alignment structures. Assembly is carried out by proprietary automated processes and equipment.

Optical fibers are not connected directly to the Si photonic substrate, but to the optical pins on a separate higher interface, which allows for a more robust and lower cost connection.
There is no need to secure an area for mounting optical fibers directly to the chip surface, thus contributing to the further miniaturization of Si photonic chips.

Overview

High Temperature operation

One of the key features of the Optical I/O Core is the optical pin structure, which couples light from the I/O Core transmitters to the multimode fiber (MMF) interface, and from the MMF interface to receivers in the I/O Core.


Variations in transmitter temperature give rise to shifts in the LD wavelength, which in turn cause changes in the angle of emission through the grating couplers. The optical pins on the transmitter side are designed to confine the light emitted from the grating couplers in their cores, even when the emission angle varies. This allows stable optical connections to be maintained even at temperatures exceeding 100 °C or higher.
The optical pins on the receiver side are tapered to efficiently capture the light from the larger multimode fiber core, and guide and compress it into the smaller active area of the photodetector.


The optical pins are largely temperature independent with a misalignment tolerance higher than ± 10 µm to mount the MMF array, which is over an order of magnitude higher than competing silicon photonics chips. The increased misalignment tolerance of the optical interface allows for a low-loss optical connection to be maintained over a longer time and under harsher conditions, thus substantially increasing the reliability of the critical optical connection.

High Temperature operation

Cost efficiency

The Optical I/O Core batch assembly process divides the Si photonics wafer into 4 x 4 (total of 16 pcs) tiles with components assembled on a tile-by-tile basis. The LDs are mounted into their I/O Core tiles through an automated alignment process using passive alignment features patterned both on the Si photonic chip and the LD. Using conventional pick-and-place techniques and equipment, this gives rise to a positional accuracy of 0.5 µm or less.
The optical pins are formed photolithographically on the 16 Optical I/O Core tiles using an automatic exposure machine with ordinary lenses, thus low cost and high productivity can be achieved.
Finally we are developing an automated assembly machine, that can mount optical fibers passively onto the Optical I/O Core. Passive automated alignment is made possible by the increased misalignment tolerance afforded by the optical pins and the MMFs. Further cost reduction is thus achieved, compared to competing single mode devices in the market, by using lower cost, lower precision MMF components instead of higher precision single mode fibers (SMF) and associated components.
If you would like to build a custom module, we can help you take advantage of this passive optical connector.

Cost efficiency
Cost efficiency