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ABOUT US

AIO CORE provides a leading-edge solution to “On-Board Optics” and “Co-packaged Optics”, where operating temperature, footprint size and power consumption are the key issues to be solved.

Our Vision

AIO Core follows the philosophy that
“Simplicity is the ultimate form of sophistication”

Our Vision

Our optical micro-transceiver solutions enable short range optical connectivity in Information Communication Technology systems spanning many applications including high performance computing, 5G+, hyperscale data centers, automotive and others.

AIO Core’s silicon photonics building blocks are capable of 25 Gbps, 32 Gbps and 50 Gbps NRZ signal transmission per channel.

Due to the proprietary AIO Core optical package solution and multimode fiber interface, these multichannel micro-transceivers can be deployed at low-cost and with low maintenance and high reliability in any ICT environment.

We draw on the advanced expertise of our team of more than twenty engineers spanning electronics, optics and packaging to offer customized solutions, which are compact, flexible, reliable and low-cost.

 

Design Concept

I/O Core is an optical micro-transceiver that integrates optical transmission and receiver functions onto a single chip. It is designed for short distance interconnections over multimode fibers.


It is, in essence, an optical building block that can be flexibly combined with optical components to form the basis of front-pluggable transceiver modules, midboard electro-optical module (EOM) and Co-Packaged Optical modules.


I/O Core can be developed at a lower cost than competing products, due to its unique and proprietary approach to miniaturization, integration and its multimode interface, which allows a reduction in component and mounting accuracy.


AIO Core is focused on computing applications where low power consumption and low latency are important. Therefore, in addition to 25 Gbps products, we are developing 32 Gbps and 50 Gbps NRZ optical I/O cores.

Positioning of Optical I/O Core

Positioning of Optical I/O Core

Multi mode & Passive termination
Easy & High productivity handling

Multi mode & Passive termination

Areas targeted by Optical I/O Core

Areas targeted by Optical I/O Core
 

Performance

Si photonics

In the MZI modulator, the expression for modulation efficiency is given by C × V (where C =Capacitance, V = supply voltage). As C is temperature independent and the modulation voltage is constant, the frequency band is stable over a wide temperature range. Therefore, a very stable optical output waveform with low jitter can be obtained over a wide temperature range.


A Quantum Dot Fabry-Perot laser is used as the light source. Quantum Dot lasers exhibit low temperature dependence in their L-I characteristics and can provide sufficient optical output even at very high temperatures. Also, it includes the feature that reflected return light noise is very small. Optical I/O Core can therefore be used over a wide temperature range. The light output waveform of the current product from -40 °C to 85 °C is shown.


When an Optical I/O Core is mounted around a logic LSI (e.g. a Co-Packaged Optical module) or used in a harsh environment, operation at 100 °C or higher may be required. We are developing an Optical I/O Core that operates at temperatures above 100 °C, and plan to release it in the near future.


The following images show an example of an optical output waveform at 100 °C.

optical output at high temperature
wide range temperature operation

Packaging

One of the key features of the Optical I/O Core is the optical pin structure, which couples light from the I/O Core transmitters to the multimode fiber (MMF) interface, and from the MMF interface to receivers in the I/O Core.


Variations in transmitter temperature give rise to shifts in the LD wavelength, which in turn cause changes in the angle of emission through the grating couplers. The optical pins on the transmitter side are designed to confine the light emitted from the grating couplers in their cores, even when the emission angle varies. This allows stable optical connections to be maintained even at temperatures exceeding 100 °C or higher.
The optical pins on the receiver side are tapered to efficiently capture the light from the larger multimode fiber core, and guide and compress it into the smaller active area of the photodetector.


The optical pins are largely temperature independent with a misalignment tolerance higher than ± 10 µm to mount the MMF array, which is over an order of magnitude higher than competing silicon photonics chips. The increased misalignment tolerance of the optical interface allows for a low-loss optical connection to be maintained over a longer time and under harsher conditions, thus substantially increasing the reliability of the critical optical connection.

Packaging
 

Cost efficiency

Si photonics

Size
The cost of an optical transceiver can be broadly divided into device and implementation. It is sometimes said that Si photonics is cheap, because it can be mass-produced by a process equivalent to CMOS, but this is not necessarily true. In the case of silicon photonic integrated circuits, cost is determined largely by the size of the chip. By reducing the size of the chip and increasing the yield, a lower cost is achieved.
In the Optical I/O Core micro-transceiver, the optical interface area is minimized by optimizing the mounting structure, and the chip area is reduced by mounting the IC and LD as bare die. The 100 Gbps micro-transceiver chip has a size of 5 mm x 5 mm, which makes it the smallest chip in the world with this function. As shown below, this size will be further reduced in the future.


Yield
Ar immersion technology is applied to 300 mm SOI wafers. The device is designed with robustness in mind. Therefore, the characteristics in the wafer are very uniform and chips can be obtained with a very high yield.
By producing smaller chips in higher yields than anywhere else, we have succeeded in significantly reducing the cost of our Si photonic chips.

Si photonics
Si photonics

Packaging

The Optical I/O Core batch assembly process divides the Si photonics wafer into 4 x 4 (total of 16 pcs) tiles with components assembled on a tile-by-tile basis. The LDs are mounted into their I/O Core tiles through an automated alignment process using passive alignment features patterned both on the Si photonic chip and the LD. Using conventional pick-and-place techniques and equipment, this gives rise to a positional accuracy of 0.5 µm or less.
The optical pins are formed photolithographically on the 16 Optical I/O Core tiles using an automatic exposure machine with ordinary lenses, thus low cost and high productivity can be achieved.
Finally we are developing an automated assembly machine, that can mount optical fibers passively onto the Optical I/O Core. Passive automated alignment is made possible by the increased misalignment tolerance afforded by the optical pins and the MMFs. Further cost reduction is thus achieved, compared to competing single mode devices in the market, by using lower cost, lower precision MMF components instead of higher precision single mode fibers (SMF) and associated components.
If you would like to build a custom module, we can help you take advantage of this passive optical connector.

Packaging
Packaging
 

Management Team

Hidetaka Fukuda

Hidetaka Fukuda

CEO

HIDE has 40 years’ experience in high-tech industries as Government Officer and Consultant, and has a wide network of contacts especially in semiconductor industry in Japan, US and Asia. He also had served as Special Advisor (Value Creation) at Silver Lake in 2008-2018.

He started his carrier at the Ministry of International Trade and Industry (MITI). He was assigned Deputy Director of JETRO at San Francisco in 1998-2001, then was Managing Director of Information and Communications Equipment Division at MITI in 2003-2005. He retired from the office in 2006.

HIDE joined AIOCORE as one of the co-founders in April, 2017. He was a board member and CSO (Chief Strategic Officer), and  is CEO from June, 2021.

Kazuhiko Kurata

Kazuhiko Kurata

CTO

KAZU had been the PETRA project leader for development “Optical I/O Core ” based on silicon photonics technology since 2012. He has over 30 years of experience and leadership in R&D and product development. He realized several optical fiber communications,optical interconnection modules and optical subsystems at the NEC Transmission Division,NEC Laboratories and PETRA. LD passive alignment technology, one of the keys of optical I/O cores, have been developed and completed with his leadership about 25 years ago.The advanced embedded optical interconnect module "PETITE" was also producted out in 2008,which is the initial stage of optical interconnection.

KAZU joined AIOCORE in April 2017 as one of its co-founders. Since then, he has served as Director and Chief Technology Officer.

Tomoyuki Fujita

Tomoyuki Fujita

CAO

TOMO had been Executive Managing Director at PETRA including Optical I/O Core group for 8 years from the beginning. In prior to PETRA He worked for NEC Research and Development Group over 30 years in the area of Computer Aided Design, Mathematical Engineering and Information Physics. He received NEC's Presidencial outstanding award 6 times.

During NEC period, he was sent to Dept. EECS, Univ. of California at Berkeley from 1983 to 1984 as a visiting researcher on VLSICAD. He also worked for NEC Labs, China at Beijing from 2003 to 2005 as Deputy Managing Director.

TOMO started up AIOCORE in April 17th of 2017 as one of the co-founders, and board member and CEO, and is CAO (Chief Administrative officer) from June, 2021.

Satoshi Mizusawa

Satoshi Mizusawa

Director

SATOSHI works for RYOSAN Co. Ltd. more than 25 years. He is basically a semiconductor Field Application Engineer ( FAE ) expert. His application field covers not only various micro-processors but also customers VLSI applications, including FPGAs and Reconfigurable Processors.
He was General Manager, Systems Solutions Division in 2014.
From 2016, he is Executive Officer,Head of Corporate Solutions Division (present post)
SATOSHI joined AIOCORE in Octber, 2017 as a director, board member.

Tomohito Takano

Tomohito Takano

Director

TOMOHITO works for I-PEX (formly called Daiichi-Seiko) Company more than 25 years. He is an expert on small connectors, and has been engaged in automatic machine design and development, research and development of connectors for consumer use.
From January 2019, he is Deputy General Manager, Electronic Components Division at I-PEX Co., Ltd. (present post)
TOMOHITO joined AIOCORE in June, 2019 as board member, director.

Koji Osawa

Koji Osawa

Director


Dr. Osawa has over thirty-five years of experience in investment and management of high-tech companies in Japan, the U.S. and Asia. He co-founded Global Catalyst Partners in Silicon Valley (U.S.) in 1999 and Global Catalyst Partners Japan (GCPJ) in 2014. GCPJ focuses on investment opportunities primarily in Japan with $120M under the management.
Prior to GCPJ, Dr. Osawa was at Mitsubishi Corporation, the largest trading firm, for 14 years, starting in 1985. He was responsible for business development with high-tech companies in Japan, U.S. and Asian countries.
Dr. Osawa is on the board of 10 portfolio companies and serves on the Board of Directors of KITO Corporation (a public company at TSE) and Keizai Silicon Valley(NPO).
Dr. Osawa received a BS in Electronics from Keio University, Japan and Ph.D. in Engineering from Tohoku University, Japan.

Masato Marumo

Masato Marumo

Corporate Auditor


Masato is a business development expert with strong financial background as a PE/VC investor. Focus on technologies such as wireless technologies, semiconductors, electronic components, IoT/AI and agritech. Over 25 years of experience in bridging Japanese blue-chips to global markets and technologies.
Masato received MBA from Harvard Business School in 1996. In prior to MBA, he worked at the Industrial Bank of Japan for 10 years.
After MBA, he worked for Carley Japan LLC, Lazrd Frehe Co. Ltd. and Silver Lake Asia LLC (Japan national team).
Currently, Masato is a President & CEO of Origin Wireless Japan Co., Ltd. and a Director of MetCom Co., Ltd., etc.
Masato is a Corporate Auditor of AIOCORE since June, 2020.

 

Company Profile

The first spin-off company from a technical research association "技術研究組合" approved by the Ministry of Economy, Trade and Industry, over 50 years history of "技術研究組合" in Japan

Company Name

AIOCORE Co., Ltd.

アイオーコア株式会社 (in Japanese representation)

Representative

President and CEO: Hidetaka Fukuda

Location

Head Office

47-12-301, Sekiguchi 1-chome, Bunkyo-ku, Tokyo, 112-0014 Japan
(Edogawa-bashi Build. 3rd floor)

Tsukuba Center

16 -1 Onogawa, Tsukuba City, Ibaraki Prefecture ( in AIST West)

Yamanashi Center

Otsuki City, Yamanashi Prefecture (In the Otsuki Plant of NECPF)

Establishment

17th of April, 2017

Business Domain

Design, development, manufacture and sales of silicon photonics integrated circuits

Head Office

 

Company History

2021.1.8

A New Coronavirus Special Loan of 400 million yen was provided by Japan Financial Corporation (JFC).

2020.6.29

AIO Core was selected by NEDO, New Energy and Industrial Technology Development Organization, as the responsible company developing the next generation optical transceiver that works in high temperature more than 100 degree C as ambient temperature applicable to millimeter wave band 5G base station. The term of project is three years.

2020.4.24

Accomplished 3rd round investment for developing mass production line of “Optical I/O Core”.

2020.2.7

A long-term loan of 400 million yen was provided by Japan Financial Corporation (JFC).

2019.3.6

Released Commercial Product of AIO Core as a result of 2nd round investment.

The products are exhibited at OFC 2019.

2018.10.1

Accomplished 2nd round investment for developing commercial product.

2018.7.24

NEDO project "Silicon-Photonics 32G Optical Transmitter/Receiver Development"

AIO CORE proposed 32 Gbps optical transceiver was accepted as a NEDO grant and started its activities.

2018.3.1

Released Engineering Sample as a result of 1st round investment.

AIO Core Announces Industry-First Ultra-Low Power and Extremely Compact Silicon Photonics Engine for 100 Gbps transceiver.

The samples are exhibited at OFC 2018.

2017.9.30

Accomplished 1st round investment for developing engineering sample.

2017.4.17

Established (Apr. 17th)

AIO CORE is the first spin-off company from a "Engineering Research Association" approved by the Ministry of Economy, Trade and Industry over 50 years history of "Engineering Research Association" in Japan

NEDO announced AIO Core establishment in their homepage.